Contemporary electronic systems are mostly composed of a plurality of integrated circuits, and each integrated circuit fulfills one or more functions. For example, a computer has at least one microprocessor and a plurality of memory circuits. Each integrated circuit usually corresponds to an electronic chip in its own “package”. The integrated circuits are soldered or inserted onto, for example, a “printed circuit board” (or “PCB”) which provides the connection between the integrated circuits.
For the last several generations of integrated circuits, the constant need to increase the density of functionality has led to systems being designed according to the “system on chip” concept. All the components and circuit blocks necessary for implementing the set of functions of the system are then produced on the same chip, without using the support of a printed circuit. In practice, it is however very difficult to obtain a high-performance “system on chip” because the methods of fabricating logic and memory circuits, for example, differ very substantially.
The “system on chip” approach therefore entails accepting a compromise between the performances of the various functions produced on the same chip. Furthermore, the size of such chips and their fabrication yield are reaching the limits of their economic viability.
Another approach consists in fabricating, in the same package, a module that provides the interconnection of a plurality of integrated circuits, which may in this case belong to the same semiconductor substrate or different substrates. The package thus obtained, a “multi-chip module” (or “MCM”), is thus in the form of a single component. There are various technologies for an “MCM” substrate, for example laminated, ceramic. In all cases, the “MCM” approach makes it possible to obtain a higher interconnection density and therefore better performance than a classical “PCB” approach. It is not, however, fundamentally different therefrom. Further to the bulk and weight of the package, the performances of an “MCM” remain limited by the parasitic elements associated with the length of the connections of the substrate and with the connection wires (“wire bonding”) joining the substrate or the chips to the “pins” of the package.
By virtue of using integration in three dimensions (3D) or vertical integration, the chips are “stacked” and are connected together by vertical interconnects. The stack obtained has a plurality of layers or strata of active components or chips, and it constitutes an integrated circuit in three dimensions (“3D integrated circuit” or “3D IC”).
The benefits of 3D integration relate simultaneously to:
(1) the improvement in performance, for example reduction of the propagation time and the power dissipated, increase in the operating speed of the system associated with accelerated communication between the functional blocks, increase in the passband of each functional block, increase in the noise immunity,
(2) the cost improvement, for example increase in the integration density, better fabrication yield owing to use of the electronic chip generation most appropriate for each functional block, increase in reliability, and
(3) the possibility of producing large-scale integrated systems by stacking heterogeneous technologies (or co-integration) i.e. employing different materials and/or different functional components.
Today, 3D integration proves to be an indispensable alternative to conventional approaches, which are reaching their limits in terms of performance, functionality diversification and production cost. After stacking, for example by adhesive bonding, the chips can be connected individually to the pins of the package by connection wires. However, mutual interconnection of the chips with a high interconnect density can be obtained only by employing through vias. The fundamentals and advantages of 3D integration have been described for example in: A. W. Topol, D. C. La Tulipe, L. Shi, D. J. Frank, K. Bernstein, S. E. Steen, A. Kumar, G. U. Singco, A. M. Young, K. W. Guarini and M. Leong, “Three-dimensional integrated circuits” IBM Journal Res. & Dev., vol. 50, No 4/5, July/September 2006, pages 491-506.
The thinning of the silicon “wafers”, the alignment between the layers, the “bonding” of the layers, the etching and the metallization of the through vias within each layer are elementary technologies necessary for the production of three-dimensional integrated circuits.
Three-dimensional integrated circuits can be produced by thinning the silicon wafer before fabricating the through vias (for example U.S. Pat. Nos. 7,060,624; 7,148,565).
The etching and metallization of the vias may also be carried out before thinning the silicon wafer (for example U.S. Pat. Nos. 7,060,624; 7,101,792). In this case the vias are etched into the silicon, then metallized to the desired depth before thinning the silicon wafer. During their metallization, the vias are therefore closed, or “blind vias”.
The good electrical conductivity of copper and its high resistance to the phenomenon of electromigration, that is to say little migration of copper atoms under the effect of the electrical current density, which is liable to be a major cause of a malfunction, make it in particular a material of choice for metallization of the through vias.
The through vias are generally produced in a similar way to the “Damascene process” (used in the field of microelectronics to fabricate elements for interconnecting integrated circuits) according to a succession of steps involving:                etching the vias into or through the silicon wafer;        depositing a layer of insulating dielectric (generally consisting of silicon oxide or nitride, for example);        depositing a barrier layer or “liner” (generally consisting of tantalum (Ta), titanium (Ti), tantalum nitride (TaN), titanium nitride (TiN), tungsten titanate (TiW) and tungsten nitride or carbide (WCN) or combinations of these metals, for example) which is used to prevent the migration of copper;        depositing a thin layer of metallic copper, referred to as a “seed layer”;        filling the vias by electrodeposition of copper; and        removing the excess copper by chemical-mechanical polishing.        
The steps of depositing the barrier layer, the seed layer, and filling and polishing the copper create the metallization of the through vias.
The barrier layer generally has too high a resistance to allow copper to be deposited homogeneously or uniformly on the wafer scale by direct electrochemical means, a phenomenon known to the person skilled in the art by the term ohmic drop. The high resistance of the barrier layer results from the high resistivity of the metals constituting it (for example metal nitrides).
Before the step of filling by electrodeposition of copper, it is therefore necessary to cover the barrier layer—by a non-electrochemical method—with a thin layer of metallic copper referred to as the seed layer.
This seed layer, like the barrier layer, is currently produced by “physical vapour deposition” or “chemical vapour deposition” processes (PVD and CVD).
Chemical vapour deposition (CVD) makes it possible to obtain a conformal layer of copper, that is to say one which accurately follows the topology of the surface to be coated, and does so for a wide range of form factors (“aspect ratios”).